The present invention relates to a circuit of a digital video signal processor and, more particularly, to a circuit of a digital video signal processor to be used in a high definition digital TV system, video CODEC's for telecommunication or the like.
In high definition digital TV systems, 3-dimensional filters with inter/intraframe processing are used as filters for separating illuminance and chrominance from composite video signals such as NTSC or PAL, in place of a band-pass filter or a 2-dimensional comb filter according to the prior art, or used as a motion-detection filter for motion compensation. Thanks to these technologies, high density informations can be extracted from composite signals, without cross-color and degradation in resolution. These technologies can also be applied to future high-definition video signal formats such as HDTV (High-Definition TV).
Now, when a motion appears in the TV frame, some problems such as cross-color, cross-illuminance or blurred edge arise from the 3-dimensional filter with inter-frame signal processing. Therefore, a motion adaptation is carried out, where the conventional 2-dimensional comb filter is used in place, in accordance with the motion in the TV frame. For this motion adaptation, a motion detection circuit for detecting motions between successive TV frames is indispendable. Basically this motion detection is carried out by calculating the difference between successive frames. However, the difference in the treatment of color and illuminance make this signal processing a little bit complex.
FIG. 2 shows an example of the prior art of a video signal processor which functions as the aforementioned motion detection circuit. A signal processing block 1' located at the lefthand side of FIG. 2 and enclosed by broken lines detects the motion. First, signals delayed several pixels, several scanning lines and several fields are fed to registers 3 from terminals IN1 to IN8. Then averaging (interpolation) and subtraction are performed by arithmetic logic units 4. Basically the motion is detected by calculating the difference between successive frames.
The output of this signal processing block 1' is fed to a transversal filter, which is exemplified by a signal processing block 2' located at the righthand side of FIG. 2 and enclosed by broken lines. This filter is used to remove the high-frequency components of the motion signal. Motion signal cannot be used unless it is filtered through the transversal filter 2', which plays an important role.
The circuit of the prior art shown in FIG. 2 is constructed of a number of ALUs, multipliers 5, registers 3, coefficient memories 7, delay memories 6 and so on. The transversal filters 2' uses a large number of components, especially in multipliers 5 and ALUs 4 about 3,000 transistors and about 1,000 transistors respectively, so that the circuit scale is enlarged to raise a problem. One of counter-measures against this problem is a method where multiplyings are performed with a lock-up table using RAMs (i.e., Random Access Memories). Even with this method, however, the number of elements or transistors used per tap of the transversal filter is still as large as about 5,000 so that the filter 2' (having a symmetrical coefficient of eight taps) of FIG. 2 has a circuit with around 40,000 transistors. This number is as large as that of a first generation 16-bit microprocessor. The high definition digital TV receiver uses as many as ten filters of this kind, so that the scale-down of these filter circuits is an important subject.
The prior art described above takes no consideration into the recent progress in the speed of the transistors, as described in the following, so that processing circuits are used without any time multiplex. Therefore the number of transistors used there is too large to implement that video system is a couple of VLSI chips.
As the VLSI fabrication technique progresses, the gate length of a MOS transistor is scaled down so that the device characteristics, especially the gate delay time gets shorter. Consequently, the critical path delay of the signal processing circuits, including multipliers and ALUs are improved. For example, the critical path delay of an 8.times.8 bit multiplier is about 50 ns with 3 .mu.m MOS transistors. This can be shortened to about 12 ns by using 0.8 .mu.m MOS transistors. On the contrary, the sampling time of a digital TV system, for example, is constant at 70 ns. The single use of the signal processing circuits for one sampling time is seriously wasteful.
In the example described above, a time multiplex of at least five times can be accomplished to reduce the number of arithmetic logic units to be used to one fifth.